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| IRFD9220 Data Sheet July 1999 File Number 2286.3 0.6A, 200V, 1.500 Ohm, P-Channel Power MOSFET This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17502. Features * 0.6A, 200V * rDS(ON) = 1.500 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Symbol D Ordering Information PART NUMBER IRFD9220 PACKAGE HEXDIP BRAND IRFD9220 G S NOTE: When ordering, use the entire part number. Packaging HEXDIP DRAIN GATE SOURCE 4-51 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFD9220 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFD9220 -200 -200 -0.6 -4.8 20 1.0 0.008 290 -55 to 150 300 260 UNITS V V A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = -250A, VGS = 0V, (Figure 9) VGS = VDS, ID = -250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC MIN -200 -2.0 -0.6 0.6 VDS = -25V, VGS = 0V, f = 1MHz, (Figure 10) Measured From the Drain Lead, 2.0mm (0.08in) From Header to Center of Die Measured From the Source Lead, 0.2mm (0.08in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S TYP - MAX -4.0 -25 -250 500 UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD VDS > ID(ON) x rDS(ON)MAX, VGS = -10V VGS = 20V ID = -0.3A, VGS = -10V, (Figures 7, 8) VDS < 50V, ID = -0.3A, (Figure 11) VDD = 0.5 x Rated BVDSS, ID 0.6A, RG = 9.1 VGS = -10V, (Figures 16, 17) RL = 165 for VDD = 100V MOSFET Switching Times are Essentially Independent of Operating Temperature. VGS = -10V, ID = -0.6A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 13, 18, 19) Gate Charge is Essentially Independent of Operating Temperature 1.000 1.500 1.0 15 25 80 50 16 10 4 350 100 30 4.0 40 50 120 75 22 - - Internal Source Inductance LS - 6.0 - nH Thermal Resistance Junction to Ambient RJA Typical Socket Mount - - 120 oC/W 4-52 IRFD9220 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX -0.6 -4.8 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TC = 25oC, ISD = -0.6A, VGS = 0V (Figure 12) TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/s TJ = 150oC, ISD = -0.6A, dISD/dt = 100A/s - 150 0.5 -1.5 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 4. VDD = 25V, starting TJ = 25oC, L = 1210mH, RG = 25, Peak IAS = 0.6A (Figures 14, 15). Typical Performance Curves 1.2 1.0 0.8 Unless Otherwise Specified -0.6 IDS, DRAIN TO SOURCE CURRENT (A) POWER DISSIPATION MULTIPLIER -0.4 0.6 0.4 -0.2 0.2 0 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE -10 -5 -10V -9V VGS = -7V VGS = -8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. ID, DRAIN CURRENT (A) -1.0 10s 100s 1ms ID, DRAIN CURRENT (A) -4 -3 VGS = -6V -2 VGS = -5V -1 VGS = -4V 0 -0.1 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) -0.01 TC = 25oC TJ = MAX RATED SINGLE PULSE -1.0 -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) 10ms 100ms DC -500 0 -10 -20 -0.002 -0.2 -30 -40 -50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS 4-53 IRFD9220 Typical Performance Curves -5 IDS, DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. -4 VGS = -7V Unless Otherwise Specified (Continued) IDS(ON), DRAIN TO SOURCE CURRENT (A) -5 VGS = -8V -3 VGS = -9V VGS = -10V -2 VGS = -6V VGS = -5V -1 VGS = -4V 0 0 -1 -2 -3 -4 -5 VDS, DRAIN TO SOURCE VOLTAGE (V) -4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS I D(ON) x rDS(ON) MAX TJ = 125oC TJ = 25oC TJ = -55oC -3 -2 -1 0 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -10 FIGURE 5. SATURATION CHARACTERISTICS 1.5 2.0s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE FIGURE 6. TRANSFER CHARACTERISTICS PULSE DURATION = 80s -2.5 DUTY CYCLE = 0.5% MAX. VGS = -10V, ID = -0.3A -2.0 ON RESISTANCE () VGS = - 10V 1.0 VGS = - 20V -1.5 0.5 -1.0 -0.5 0 0 -1 -2 -3 -4 -5 0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) ID, DRAIN CURRENT (A) NOTE: Effect of 2.0s pulse is minimal. FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.15 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.10 1.05 1.00 0.95 0.90 0.85 -80 C, CAPACITANCE (pF) 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD CISS 400 300 200 COSS CRSS 100 -40 0 40 80 120 160 0 0 -10 -20 -30 -40 -50 TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4-54 IRFD9220 Typical Performance Curves 4 gfs, TRANSCONDUCTANCE (S) VDS ID(ON) x rDS(ON)MAX PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. TJ = -55oC TJ = 25oC 2 TJ = 125oC ISD, DRAIN CURRENT (A) Unless Otherwise Specified (Continued) -100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 3 -10 TJ = 150oC -1.0 TJ = 25oC 1 0 0 -1 -2 -3 I D , DRAIN CURRENT (A) -4 -5 -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE 0 ID = -3.6A VGS, GATE TO SOURCE (V) -5 -10 VDS = -40V VDS = -100V VDS = -160V -15 -20 0 4 8 12 16 20 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + 0V VGS DUT tP IAS 0.01 VDD VDD IAS tP BVDSS VDS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS 4-55 IRFD9220 Test Circuits and Waveforms (Continued) tON td(ON) tr RL 0 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR -VDS (ISOLATED SUPPLY) 0 DUT VDS 12V BATTERY 0.2F 50k 0.3F Qgs D G DUT VDD Qgd Qg(TOT) VGS 0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 IG(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-56 |
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